naps.util package¶

Submodules¶

naps.util.draw_hierarchy module¶

naps.util.draw_hierarchy.hierarchy_to_dot(e: nmigen.hdl.ir.Elaboratable, plat=None, **kwargs)¶

naps.util.formal module¶

naps.util.formal.assert_formal(spec, mode='bmc', depth=1)¶

naps.util.nmigen_misc module¶

naps.util.nmigen_misc.assert_is_pot(x)¶

naps.util.nmigen_misc.connect_leds(m, platform, signal, upper_bits=True)¶

naps.util.nmigen_misc.delay_by(signal, cycles, m)¶

naps.util.nmigen_misc.ends_with(signal, *patterns)¶

naps.util.nmigen_misc.iterator_with_if_elif(iterator: Iterable, module: nmigen.hdl.dsl.Module) → Iterator¶: A helper to build a priority encoder using If / Elif constructs :param iterator: the iterator contaianing all the elements :param module: the module from which m.If and m.Elif are sourced

naps.util.nmigen_misc.log2(x)¶

naps.util.nmigen_misc.max_error_freq(real_freq, requested_freq, max_error_percent=1)¶

naps.util.nmigen_misc.nAbsDifference(a, b)¶

naps.util.nmigen_misc.nAll(seq)¶

naps.util.nmigen_misc.nAny(seq)¶

naps.util.nmigen_misc.nAvrg(*values)¶

naps.util.nmigen_misc.nMax(a, b)¶

naps.util.nmigen_misc.nMin(a, b)¶

naps.util.nmigen_misc.with_reset(m, signal, exclusive=False)¶

naps.util.nmigen_misc_test module¶

class naps.util.nmigen_misc_test.TestNMigenMisc(methodName='runTest')¶

Bases: unittest.case.TestCase

test_ends_with()¶

test_is_pot()¶

test_log2()¶

test_nAbsDifference()¶

test_nAll()¶

test_nAny()¶

test_nMax()¶

test_nMin()¶

naps.util.plot_util module¶

naps.util.plot_util.plt_discrete_hist(title, data)¶

naps.util.plot_util.plt_hist(title, data, **kwargs)¶

naps.util.plot_util.plt_image(title, data, **kwargs)¶

naps.util.plot_util.plt_show()¶

naps.util.python_misc module¶

naps.util.python_misc.camel_to_snake(name)¶

naps.util.python_misc.decimal_range(start, stop, step)¶

naps.util.sim module¶

class naps.util.sim.FakeResource(name, handed_out_resources)¶

Bases: nmigen.hdl.ast.UserValue

lower()¶: Conversion to a concrete representation.

class naps.util.sim.SimPlatform(filename=None)¶

Bases: object

add_file(name, contents)¶

add_process(generator, domain=None)¶

add_sim_clock(domain_name, frequency)¶

prepare(top_fragment, name='top', *args, **kwargs)¶

request(name, number=0)¶

sim(dut, testbench=None, traces=(), engine='pysim')¶

class naps.util.sim.TristateIo(shape=None)¶: Bases: object

naps.util.sim.do_nothing(length=10)¶

naps.util.sim.pulse(signal, length=1, after=0)¶

naps.util.sim.resolve(expr)¶: Resolves a nMigen expression that can be constantly evaluated to an integer

naps.util.sim.wait_for(expr, timeout=100, must_clock=True)¶

naps.util.size_estimation module¶

naps.util.size_estimation.get_module_sizes(module, *args, **kwargs)¶

naps.util.size_estimation.print_module_sizes(module, *args, **kwargs)¶

naps.util.yosys module¶

naps.util.yosys.get_verilog_module_ports(verilog_paths, module_name)¶

Get the ports of a verilog module via yosys

Parameters

verilog_paths –
module_name –

Returns

the verilog as a string

naps.util.yosys.parse_yosys_json(verilog_paths)¶

naps.util.yosys.yosys_script(commands)¶

Executes a yosys script

Parameters: commands – a list of commands to run
Returns: the stdout of yosys