naps.soc.platform.zynq package¶
Submodules¶
naps.soc.platform.zynq.memory_accessor_devmem module¶
-
class
naps.soc.platform.zynq.memory_accessor_devmem.DevMemAccessor(base_addr=1073741824, bytes=None, filename='/dev/mem')¶ Bases:
object-
mask= -4¶
-
read(offset)¶
-
word= 4¶
-
write(offset, to_write)¶
-
-
naps.soc.platform.zynq.memory_accessor_devmem.MemoryAccessor¶ alias of
naps.soc.platform.zynq.memory_accessor_devmem.DevMemAccessor
naps.soc.platform.zynq.to_raw_bitstream module¶
-
naps.soc.platform.zynq.to_raw_bitstream.bit2bin(bitstream, flip_data=True)¶
-
naps.soc.platform.zynq.to_raw_bitstream.flip32(data)¶
naps.soc.platform.zynq.zynq_soc_platform module¶
-
class
naps.soc.platform.zynq.zynq_soc_platform.ZynqSocPlatform(platform, *args, **kwargs)¶ Bases:
naps.soc.soc_platform.SocPlatform-
base_address= 0x40000000[0:8589934584]¶
-
csr_domain= 'axi_lite'¶
-
pack_bitstream_fatbitstream(name: str, build_products: nmigen.build.run.BuildProducts)¶
-
program_fatbitstream(*args, **kwargs)¶
-
pydriver_memory_accessor= "import mmap\nimport os\nimport struct\nfrom math import ceil\n\n\nclass DevMemAccessor:\n word = 4\n mask = ~(word - 1)\n\n def __init__(self, base_addr=0x4000_0000, bytes=None, filename='/dev/mem'):\n if bytes is None:\n bytes = mmap.PAGESIZE\n\n assert (base_addr % mmap.PAGESIZE) == 0\n\n bytes = int(ceil(bytes / mmap.PAGESIZE) * mmap.PAGESIZE)\n\n self.base = base_addr\n\n self.f = os.open(filename, os.O_RDWR | os.O_SYNC)\n self.mem = mmap.mmap(self.f, bytes, mmap.MAP_SHARED, mmap.PROT_READ | mmap.PROT_WRITE, offset=base_addr)\n\n def __del__(self):\n os.close(self.f)\n\n def read(self, offset):\n self.mem.seek(offset)\n return struct.unpack('I', self.mem.read(4))[0]\n\n def write(self, offset, to_write):\n self.mem.seek(offset)\n return self.mem.write(struct.pack('I', to_write))\n\n\nMemoryAccessor = DevMemAccessor\n"¶
-