naps.cores.axi package

Submodules

naps.cores.axi.axi_endpoint module

class naps.cores.axi.axi_endpoint.AxiAddressStream(addr_bits, lite, id_bits, data_bytes, src_loc_at=1)

Bases: BasicStream

class naps.cores.axi.axi_endpoint.AxiBurstType(value)

Bases: Enum

FIXED = 0

INCR = 1

WRAP = 2

class naps.cores.axi.axi_endpoint.AxiDataStream(data_bits, read, lite, id_bits, src_loc_at=1, **kwargs)

Bases: BasicStream

class naps.cores.axi.axi_endpoint.AxiEndpoint(*, addr_bits, data_bits, lite, id_bits=None, src_loc_at=1, **kwargs)

Bases: Bundle

static like(model, lite=None, name='axi', **kwargs)

Create an AxiInterface shaped like a given model. :param name: the name of the resulting axi port :type model: AxiEndpoint :param model: the model after which the axi port should be created :param lite: overrides the lite property of the model. Only works for creating an AXI lite inteface from an AXI full bus. :return:

class naps.cores.axi.axi_endpoint.AxiProtectionType(backing_signal=None, name=None, src_loc_at=1, **kwargs)

Bases: PackedStructBaseClass

is_instruction: unsigned(1)

privileged: unsigned(1)

secure: unsigned(1)

class naps.cores.axi.axi_endpoint.AxiResponse(value)

Bases: Enum

DECERR = 3

EXOKAY = 1

OKAY = 0

SLVERR = 2

class naps.cores.axi.axi_endpoint.AxiWriteResponseStream(lite, id_bits, src_loc_at=1, **kwargs)

Bases: Stream

naps.cores.axi.full_to_lite module

class naps.cores.axi.full_to_lite.AxiFullToLiteBridge(*args, src_loc_at=0, **kwargs)

Bases: Elaboratable

elaborate(platform)

naps.cores.axi.interconnect module

class naps.cores.axi.interconnect.AxiInterconnect(*args, src_loc_at=0, **kwargs)

Bases: Elaboratable

elaborate(platform)

get_port()

Gets a AXI master port connected to the master via this interconnect.

Returns:

A new AxiInterface shaped after the upstream port.

naps.cores.axi.peripheral_connector module

class naps.cores.axi.peripheral_connector.AxiLitePeripheralConnector(*args, src_loc_at=0, **kwargs)

Bases: Elaboratable

elaborate(platform)

naps.cores.axi.sim_util module

naps.cores.axi.sim_util.answer_read_burst(axi: AxiEndpoint, memory: Dict[int, int], timeout=100)

naps.cores.axi.sim_util.answer_write_burst(axi: AxiEndpoint, timeout=100)

naps.cores.axi.sim_util.axi_ram_sim_model(platform: SimPlatform, domain='sync')

naps.cores.axi.sim_util.axil_read(axi, addr, timeout=100)

naps.cores.axi.sim_util.axil_write(axi, addr, data, timeout=100)

naps.cores.axi.stream_reader module

class naps.cores.axi.stream_reader.AxiReader(*args, src_loc_at=0, **kwargs)

Bases: Elaboratable

elaborate(platform)

naps.cores.axi.stream_reader_test module

class naps.cores.axi.stream_reader_test.TestAxiReader(methodName='runTest')

Bases: TestCase

test_basic()

test_burster_stream_output()

test_reader_stream_output()

naps.cores.axi.stream_writer module

class naps.cores.axi.stream_writer.AxiWriter(*args, src_loc_at=0, **kwargs)

Bases: Elaboratable

elaborate(platform)

naps.cores.axi.stream_writer_test module

class naps.cores.axi.stream_writer_test.TestAxiWriter(methodName='runTest')

Bases: TestCase

test_basic()

test_burster_address_output_stream_contract()

test_burster_data_output_stream_contract()

test_packetizer_output_stream_contract()

naps.cores.axi.zynq_util module

naps.cores.axi.zynq_util.if_none_get_zynq_hp_port(maybe_axi_port, m, platform) → AxiEndpoint

If maybe_axi_port is None, grab an AXI HP port from the zynq and return it. Otherwise returns the passed in AXI port.

Module contents