naps.cores.mipi.csi_rx package

Submodules

naps.cores.mipi.csi_rx.aligner module

class naps.cores.mipi.csi_rx.aligner.CsiWordAligner(*args, src_loc_at=0, **kwargs)

Bases: Elaboratable

A timeout based word aligner. Issues a bitslip request to the PHY if for a specified time no valid packet (as indicated by a upper layer) was received.

elaborate(platform)

naps.cores.mipi.csi_rx.combiner module

class naps.cores.mipi.csi_rx.combiner.CsiLaneCombiner(*args, src_loc_at=0, **kwargs)

Bases: Elaboratable

Combines 1 to 4 lanes to a 32 bit word that can be used for parsing the packet header. Also assists with the training of multiple lanes.

elaborate(platform)

naps.cores.mipi.csi_rx.packet module

class naps.cores.mipi.csi_rx.packet.CsiPacketLayer(*args, src_loc_at=0, **kwargs)

Bases: Elaboratable

elaborate(platform)

naps.cores.mipi.csi_rx.s7_rx_phy module

class naps.cores.mipi.csi_rx.s7_rx_phy.MipiClockRxPhy(*args, src_loc_at=0, **kwargs)

Bases: Elaboratable

Drives the sync domain with the word clock and produces a ddr bit clock derived from the clock lane at pin

elaborate(platform)

class naps.cores.mipi.csi_rx.s7_rx_phy.MipiLaneRxPhy(*args, src_loc_at=0, **kwargs)

Bases: Elaboratable

elaborate(platform)

naps.cores.mipi.csi_rx.types module

class naps.cores.mipi.csi_rx.types.CsiLongPacketDataType(value)

Bases: IntEnum

RAW10 = 43

RAW12 = 44

RAW14 = 45

RAW6 = 40

RAW7 = 41

RAW8 = 42

class naps.cores.mipi.csi_rx.types.CsiShortPacketDataType(value)

Bases: IntEnum

FRAME_END = 1

FRAME_START = 0

LINE_END = 3

LINE_START = 2

Module contents