naps.cores.peripherals package

Submodules

naps.cores.peripherals.bitbang_i2c module

class naps.cores.peripherals.bitbang_i2c.BitbangI2c(*args, src_loc_at=0, **kwargs)

Bases: Elaboratable

elaborate(platform: SocPlatform)

naps.cores.peripherals.bitbang_spi module

class naps.cores.peripherals.bitbang_spi.BitbangSPI(*args, src_loc_at=0, **kwargs)

Bases: Elaboratable

elaborate(platform: SocPlatform)

naps.cores.peripherals.csr_bank module

class naps.cores.peripherals.csr_bank.CsrBank(*args, src_loc_at=0, **kwargs)

Bases: Elaboratable

elaborate(platform)

reg(name: str, signal: _Csr)

naps.cores.peripherals.csr_bank_zynq_test module

class naps.cores.peripherals.csr_bank_zynq_test.TestAxiSlave(methodName='runTest')

Bases: TestCase

check_csr_bank(num_csr=10, testdata=305419896, use_axi_interconnect=False)

test_csr_bank_aggregator()

test_csr_bank_interconnect()

test_simple_test_csr_bank()

naps.cores.peripherals.drp_bridge module

class naps.cores.peripherals.drp_bridge.DrpBridge(*args, src_loc_at=0, **kwargs)

Bases: Elaboratable

elaborate(platform: SocPlatform)

class naps.cores.peripherals.drp_bridge.DrpInterface(DWE, DEN, DADDR, DI, DO, DRDY, DCLK)

Bases: object

naps.cores.peripherals.mmio_gpio module

class naps.cores.peripherals.mmio_gpio.MmioGpio(*args, src_loc_at=0, **kwargs)

Bases: Elaboratable

elaborate(platform)

naps.cores.peripherals.soc_memory module

class naps.cores.peripherals.soc_memory.SocMemory(*args, src_loc_at=0, **kwargs)

Bases: Elaboratable

A memory that can be read / written to by the soc

elaborate(platform)

handle_read(m, addr, data, read_done)

handle_write(m, addr, data, write_done)

read_port(*args, **kwargs)

write_port(*args, **kwargs)

naps.cores.peripherals.soc_memory_test module

class naps.cores.peripherals.soc_memory_test.SocMemoryTest(methodName='runTest')

Bases: TestCase

test_smoke()

test_with_driver()

test_with_driver_simple()

Module contents